flipflop is designed for 1.65V to 5.5V VCC operation. The RSH4013L have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ̅ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-toHIGH clock transition, is stored in the flip-flop and appears at the nQ output.
The RSH4013L dual positive-edge-triggered D-typeflipflop is designed for 1.65V to 5.5V VCC operation.
The RSH4013L have individual data (nD), clock (nCP),set (nSD) and reset (nRD) inputs, and complementarynQ and nQ̅ outputs. Data at the nD-input, that meetsthe set-up and hold time requirements on the LOW-toHIGH clock transition, is stored in the flip-flop andappears at the nQ output.
The RSH4013L is fully specified for partial-powerdown applications using Ioff. The Ioff circuitry disablesthe outputs, preventing damaging current backflowthrough the device when it is powered down.
This device available in Green SOP14 packages. Itoperates over an ambient temperature range of -40°Cto +125°C.
